The experience of applying an advanced version of Spurious Power Suppression Technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of multipliers after the data transition. The SPST has been applied on both the modified Booth decoder and the compression tree of multipliers to enlarge the power reduction. The simulation results show that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a 40% speed improvement.Adopting a 0.18µm CMOS technology, the proposed SPST - equipped multiplier dissipates only 0.0121 mW per MHz in H.264 texture coding applications, and obtains a 40% power reduction. Depending on the particular device, the program is either burned in permanently or semi permanently as part of a board assembly process, or a loaded from an external memory, each time the device is powered up.

Dr Sidharthan V is Assistant Professor, Department of Electronics, Sri Ramakrishna College of Arts and Science, Coimbatore. Has a decade of teaching experience and produced one research candidate under VLSI System Design. Recently finished the doctorate from the Bharathiar University. The area of interest includes communication systems.